Incremental computing apparatus



Aug. 21, 1962 F, G. STEELE INCREMENTAL COMPUTING APPARATUS Filed Sept. l5, 1957 8 Sheets-Sheet 1 Aug. 21, 1962 F. G. STEELE INcmnENTAL COMPUTING APPARATUS 8 Sheets-Sheet 2 Filed Sept. 16, 1957 wmwm Aug. 21, 1962 F. G. STEELE 3,050,251

INCRMENTAL COMPUTING APPARATUS Filed sept. 1e. 1957 s sheets-sheet s Aug. 21, 1962 F, G. STEELE 3,050,251

INCREMENTAL COMPUTING APPARATUS Filed sept. 1e, 195'? s sheets-sheet 4 8 Sheets-Sheet 5 F. G. STEELE INCREMENTAL COMPUTING APPARATUS Aug. 21, 1962 Filed sept. 1e, 1957 mv i...

8 Sheets-Sheet 6 F. G. STEELE INCREMENTAL COMPUTING APPARATUS Pig Aug. Y21, 1962 Filed Sept. 16, 1957 Aug. 21, 1962 F. G. STEELE mem/1mm. COMPUTING APPARATUS 8 Sheets-Sheet 8 WWW-WWW continued computation. Restoring computation is rathe easily accomplished in a GP by storing all constants in VVa permanent memory which cannot be changed and by using a programmed computation which does not utilize previously computed values of variables, but generates all Variablesanew at each computation, from the sampled values of the input quantities. j Such full restoration is, in a DDA,.very diiicult to provide, since in the very nature of DDA computation numbers are not formed anew but are only modified slightly at each iteration inz Vaccordance with applied input increments.

Another commonly comparedfeature of DDA and GP computers is the relative ease with which a program code canbeprepared by untrained personnel. In the use of a DDA, it is usually relatively easy to go directly from the mathematical formulation ofthe problem to a diagram which specifies the-required interconnection of integrators. On the other hand, in coding a GP computer it is necessary to preparea long list of detailedrstep by step instructions which are quite'remote from the broad features of the mathematical formulation. Thus, the DDA appears to have aV very real advantage in, this respect.

YThe present invention provides a new type of incremental computer which embodies some of the best features of the DDA and GPY computers. Asrin a DDA, numbers are permanently grouped together, stored in elemental computing blocks, which receive applied input i11- crements and produce corresponding output increments.

Computation is programmed through simple interconnection of computing blocks for the communication of increments between blocks. The equipment requirements of the incremental computer of the present invention are, therefore, about as low as those of a DDA computer. In addition, the ease of program preparation, common to DDAs, is retained and even enhanced in the incremental computer of the present invention. f

However, in addition, some of the very best features 5 bers is appliedand in response thereto the highest order digit of each of the output number answers is formed. In the second operation interval z', the second highest order digit of each of the input numbers is `applied and the corresponding digit of each ofthe output number v answers is formed. In continued operation, in response to each successively scaled digit of the input numbers, the correspondingly scaled output digits are formed. The fact thatthe highest order digits of answers are formed iirst and are not subject to change upon subsequent pro duction of lower order digits appears to be unique to the present computational system and offers the'very great advantage that a computation may be begun as soon as the first digits of the input numbers are entered and will -be completed lat the very time that entry of the last digi of the input numbers has been completed. Y

-In a preferred Vembodiment of the invention, as willbe explained hereinbelow, each 4computing block contains a Y number and an R number, Vand in each operation in terval i receives successively scaled input digits or increments AX and AYi, modiiies its Y and R numbers in accordance with these increments, and produces correspondingly scaled outputrincrements AZi. The successive increments have sign and magnitude il or O and have the successive scales 2 1, 2r2, 2:"3, etc. (thus having the scale 2- in the ith operation interval). These increments,

thus represent, as will be. fully explained, the successive digits of numbers expressed in a trinary number system. AY, input increments are Yadded to the Y number, the predetermined scaling .of the increment being accomplished by adding each successive increment to a succesof GP computation are retained in the incremental computer of the present invention. Although accomplished through purely incremental operations, all ordinary arithmetic operations upon numbers may be accomplished at speeds equal or superior to the speed of GP computation; and ,if desired, fully restoring computations may be'pro#V grammed in which transient errors areinevitably corrected. i

According to the underlying mathematical foundations of the present invention Vis is recognized that the digits of a number merely represent successively scaled increments fwhose summation equals the number. For example, in thedecimal number .531, the digits +5, +3

. and +1 represent the sign and magnitude of the successive scaled increment 5'10-1, 3102, and ll03 whose `sum equals 53%000. Similarly, in the binary number .110, the successive digits +1, +1, and -0 represent the successively scaled lincrements +1 21, +122, and +023 whose sum equals According to the basic concept of the present invenfor operating upon input increments which regularly vary in scale, to accordingly modify numbers stored Within the g computingiblocks and to produce correspondingly scaled output increments. More particularly, theV computing Yblocks of the present invention are adapted for operating in a regular fashion upon successively applied digits of numbers, the successivedigits of each number being treated'as successively scaledY increments of the'number. It is shown that through appropriate interconnection of elemental Ycomputing blocks, all arithmetic operations upon numbers may be carried outV through purely incremental 40 the AX input increments is accomplished by regularly 5G performance of multiplication ofrtwo numbers A0 and v sively lower order digit position of the Y number. The AX, input increments are used as multipliers of a function `g(Y, AY), the multiplied function g(Y, AY)AX, beingadded to the R number. The predetermined scaling of doubling therR number. kThe output increments AZ, are formed in such a manner that K f Y I ziziegurtraixi]+RW? I 1 Y K where AZ,.AX and AYiiare increments that are succes-Y sively halved in scale.

1. YAn example is provided hereinbelow of the interconnection of assemblages of such computing blocks for the B0, .each supplied as a sequence of successively scaled digits or increments A(A0)i and A(B0)i. The product 1 AOBO ismcrementally formed in accor-dance with the re.-

lationship t tion, `computing blocks are provided which are adapted W Another example is provided in which a number A0 provided as a sequence of successively scaled digits is multiplied iby a constant A1 stored in the Y register of a computing block and has added thereto another constant B1 stored in the R register of the block, the output digits formed by this operation being similarly operated upon by constants A2, B2, A3, B3, etc. stored in successive computing blocks. A final result of the form v expansions can be advantageously refritten in a product` is formed. This is an especially useful type of computation, since it can be'shown that almost all power series expansion of the abovedescribed type; In addition, if all constants B1, B2, B3, etc.=0,.the`n the abovedescr-ibed computation resolves to the simple cascaded multiplication l). Aj.V Y

Itis an object of the present invention fto provide incremental computing apparatus tor operating upon successively applied input increments of varying scale to produce resultant output increments similarly varying in scale.

It is another object of the present invention to provide incremental computing apparatus yfor operating upon input signals representing the highest order digits of a plurality of input number-s to produce output signals representing the highest order digit of the result of a predetermined mathematical operation upon the input numbers.

It is another object of the present invention to provide computing apparatus of the abovedescribed type which is adapted for further operating upon signals representing the highest order digit of a result 'of a mathematical operation to produce output signals representing the highest order digit ot a `further resuit of a predetermined mathematical operation upon the rst named result.

Itis still another object of the present invention to provide incremental computing apparatus of the described type which is `similarly responsivevto sequentially applied input -signals representing corresponding successively lower order digits of input numbers for sequentially producing output signals representing corresponding successively lower order digits of the result of a predetermined mathematical operation upon the input numbers.

Y It is still another object of the present invention to provide an incremental computing block responsive to sequentially applied successively scaled input increments AX1 and AY1 for sequentially modifying stored Y and R numbers in accordance with the applied input increments and for sequentially producing corresponding successively scaled increments AZ1, whose summation represents a predetermined mathematical function of the input increments. applied successively halved-in-scale input increments AX1 It is another object of the present invention to provide an incremental computing block responsive to sequentially and AY1, for adding each successive AY increment to successively lower order digit position oi the Y number and for sequentially producing corresponding successively halved-in-scale output increment A21 whose summation is proportional to the summation It is still another object tof the present invention to provide an incremental computing block having stored Y and R numbers and responsive to sequentially applied successively halved-in-scale input increments AX1 and AY1 for sequentially modifying the stored numbers and producing correspondingly scaled AZ1 output increments, proper weight being given to each successive AX increment by `successively doubling the R number and proper weight being given to each successive AY1 increment by adding each successive AY increment to successively lower order `digit positions of the Y number.

It is yet another object of the present invention to provide apparatus for performing a predetermined mathematical operation upon input numbers and comprising a plurality of incremental computing blocks having their inputs and outputs interconnected in accordance with the predetermined mathematical operation.

It is still another object of the present invention to provide incremental computing apparatus for multiplying two numbers A and B represented respectively by a 1st sequence of successively sca-led input increments AA1 and a second sequence of corresponding successively scaled input increments AB1 by combining each pair of corre'- sponding input increments to produce a correspondingly scaled output increment A(AB)1.

It is yet another object of the present invention to provide incremental computing apparatus tor multiplying two numbers A `and B by producing a irst sequence of successively scaled input increments AA1 representing successive digits of the number A, producing `a `second sequence of successively scaled input increments AB1 representing successive digits of the number B, and combining each pair of 'correspondingly scaled increments AA1 and AB1 to pro- 6 duce a resultant sequence of corresponding successively scaled output increments A(AB)1 representing successive digits of the product AB in accordance with the relation- A(AB)1`=AA1ABil-1AB1+B1AA1. Y

It is still another object of the present invention to prorvide cyclically operable incremental computing apparatus ttor multiplying a. number A1 stored in a register, by a number A0 whose successively lower order digits are represented by lsequentially applied successive decreasingly scaled input increments A(A0)1, to produce in response to each input increment a correspondingly scaled output increment A21, the `successive output increments AZ1 representing respectively the ysuccessive `digits ot fthe product AOAI.

It is yet another object of the present invention to provide an interconnected assemblage of computing blocks for storing a plurality of constants A1, A2 A1 and responsive to the highest order digit or an input number A0 for forming the highest order digit of the product A0A1A2 A1.

It is an additional object of the present invention to prov-ide an interconnected assemblage of computing blocks tor storing a plurality of constants A1, B1, A2, B2 etc., and responsive to the highest order digit of an input number A0 for forming the highest order digit of the quan'ftyt [(AoAl-I-BilAz-I-B2l etc. l.

The novel Ifeatures which are believed to be character- -istic `of the invention both as to its organization and method of operation, together with iur-ther objects and advantages thereof will be better understood trom the tfollowing description considered in connection with :the accompanying drawings in which a specific embodiment of the `invention is illustrated by way of example. It is to be expressly understood, however, thatV the drawings are provided vfor purposes of illustration and description only and are not intended as a `deiinition yor" the limits of the invention.

FIG. l is a block diagram ot an embodiment of an elemental compu'tlng block in accordance with the present invention.

FIG. 2 is a partly block-partly circuit diagram of an assemblage of computing blocks interconnected for the performance of a plurality of -cascaded mul-tiplications and/or additions.

FIG. 3 is `a partly block-partly circuit diagram of another assemblage iof computing blocks interconnected for the multiplication of two numbers respectively represented as two corresponding sequences of sequentially applied ysuccessively scaled increments.

FIG. 4 is a schematic and circuit diagram of an embodiment of a source of setting signals, utilized in the control of the assemblages of computing blocks shown in FIGS. 2 and 3.

FIG. 5 is a drawing of a suitable embodiment of a source of timing signals, utilized inthe control of the assemblages of computing blocks shown in FIGS. 2 and 3.

FIG. 6a is a circuit diagram of an embodiment of a summer circuit contained in the elemental computing block shown in FIG. l.

FIG. 6b is a partly block-partly circuit diagram showing embodiments of a Y register and an associated Y gating matrix utilized in the computing block of FIG. l.

FIG. 6c is a partly block-partly circuit diagram of embodiments of an R register, a AZ register, and an associated R gating matrix utilized in the computing block of FIG. l.

FIGS. 7, -8, 9 and V10 consisting of FIGS. 7a through 7j, 8a through 8j, 9a through 9e and 10a through 10e, are waveform charts illustrating signals appealing in various modes of operation of the assemblages of computing blocks shown in FIGS. 2 and 3.

Referring now to the drawings, there is shown in FIG. 1 a block diagram of a computing block 10, according to the invention, which contains two registers, a Y

Yment AZ, is formed. clature, the Y and R numbers stored in a computing register and an R register for storing respectively a rst number designated the Y number and a second number designated the R number in permanent association with each other, and which is operable in response to incremental inputs designated AX and AY for modifying the Y and R numbers and for producing corresponding incremental outputs designated AZ which can be communicated to other similar computing blocks to serve there as AX and AY inputs. As will be hereinafter described, the computing block shown in FIG. 1 is adapted for operating upon a sequence of incremental inputs which regularly vary in scale, the computing block modifying the stored Y and R numbers in full conformity with the changing scale of the input increments, and producing'AZ output increments which correspondingly change scale. As will -be demonstrated hereinbelow, many computational operations and in particular all arithmeticoperations can be accomplished through appropriate interconnection of elemental computing blocks.

As shown in FIG. l, computing block is adapted Vfor receiving certain setting signals SS which may be utiliz/ed periodically, at the beginning of a sequence of computational operations, to set desired initial Values of the Y and R numbers into Vthe Y and R registers. Such setting signals may be applied from auxiliary storage registers or other suitable source of number representing signals. Computing block 10 is also adapted for receiving certain timing signals TS Which are utilized to sequence successive operations of the computing block, as will be hereinafter described.

It will be understood hereafter that a single computational operation of a block 10 comprises the reception of a AX input and a AY input and the formation of a corresponding AZ output. In the operation of a computing block, initial values are periodically setinto the computing block. After each setting of initial values, an iteration or sequence of n (a predetermined integer) computational operations is performed. IFor purposes of convenient reference the successive operations performed Vduring a sequence are designated as operations (Where i has the successive values 1, 2, 3, 4 n). Similar nomenclature is fused to designate the input and output increments. During -any operation i, va corresponding AX input increment AX, is received; one or more AY input increments 'A1Y1, AZYi etc. may be received; and a corresponding AZ output incre- In accordance with this nomenblock at'the' Vbeginning of an operation i are designate as numbers Y1 and Ri. Y

The embodiment of computing block 10 shown in FIG. 1 includes, in addition the Yand R registers, the following elements: a computing circuit 12 which is seen to include an R gating matrix 14 and a'Y gating matrix 16, the computing circuit intercoupling the Y and R registers and lbeing utilizable for operating upon the i numbers in those registers in accordance with the applied AX and AY increments; a summation network 18 which is operable` for summing the applied increments A1Y1, A2Y1, etc. to form a total increment AY! which is supplied to Y gating matrix 16; and a AZ register 20 Which is adapted for receiving and storing each AZ, increment as it is formed and for communicating these increments to other computing blocks 10. In any assemblage of computing blocks 10, the AZ Iregisters 20 may be thought of Y as comprising a single common register for storage of AZ incrementsa common register from which each computing block 10 may obtain desired VAZ increments to serve as its AX and AY inputs.

As indicated in FIG. 1, thetotal increment AY, is

applied to Y gating matrix 16, which also receives over an inputibus 22., signals supplied by thewY register which Vrepresent the numberYi stored therein. 'In each operationV i, in-resp'onse to these inputs, Y gating matrix 16 8 forms signals representing a modified Y number, VWhichare applied back to the Y register along an input bus 24 to store therein the next Y number, designated Yin. The new number Yi+1 is deiined as a predetermined function f(Y1, AYi) of the inputs to Y gating matrix 16. Matrix 16 also forms signals representing anotherpredetermined function g(Y1, AY) which is applied to R gating matrix 14 over an input bus 25 thereof.

In similar manner R gating matrix 14 receives, during each operation i, the applied increment AXi, the signals representing g(`Y1, AYi), and (over an input bus 26) signals representing the number R1 stored in the R register, and in response to these inputs applies signals back to the R register, over an input bus 27, to store therein a new modified R number RM1, and also applies signals to AZ register 20 to store therein a resultant AZ increment AZi.

According to the preferred embodiment of the invention, during each successive operation i of a computational sequence, the applied input increments AX, and AlYi, A2Yi, etc., have one half the scale that they had during the preceding operation, and the outputrincrements Zi are similarly halved in scale at each successive timing interval. More particularly, in a preferred emr bodiment of the invention, which is described hereinbelow, all increments during the ith operation are restricted to the values 'gill or (abbreviatedi-lg) where z'=l, 2, n. Thus, in a computational sequence, during the iirst operation, the AX increment (and other increments) may assume the values i-/z or 0, and during the second operation may assume the values l or 0, and so forth. As will readily be appreciated, any number (scaled between Y-i-l and -1) may be represented by such a sequence or stream of increments and, as Will be shown, this makes possible the accomplishment of most ordinary arithmetic operations upon numbers, by purely incremental operations upon such sequences or streams of three valued increments.

The following notation will be used in connection with`Y the Vdesignation of these increments. The scaled values or 0) of these increments will be denoted by the underlining of these same symbols-as AX1, AYi, AZi, Etc.

Scaled three valued increments, as described hereinabove, will be designated as trinary represented increments, and sequences or streams of successively scaledV tn'nary increments will be designated as a trinary sequence or stream. When such a sequence is used to represent a number, it will be said that the number is represented in -tm'nary notation or that it is a trinary number. Thus, for example, the sequence of successively presented trinary increments of absolute value 0, 0,' +1, -1 is a representation of the number +1/6 (since %`+%I1/s1A6=-{%6). It is clear that the successive 'trinary increments can be considered to be digits, presented highest order `digit first, of a trinary number Arepresentng |J76.

To facilitate the formation of trinary increments and also to conserve storage space, in the preferred embodiment of the invention, numbers are normally maintained or stored in the Y and R registers of each computing block l0 in a modified dinary notation.

lIn -true dinary representation each successive digit of a number is represented by a `single bivalue signal having y where in the calculated Yd number each is considered to have or is replaced by the value =1. For example, to recalculate the dinar-y number representing 44%; begin with the ordinary binary number Yb=e6=+-oo11oo (2) and then calculate rcp-liga@ =.1o01/100 (a) In the calculated Yd, if each 0 digit is considered to have an appropriately scaled Value of 1, it is seen that the rst four digits of Yd are the required dinary digits of the number -l-e and that all digits beyond the fourth cancel each other and may be disregarded.

In the Y -and R registers of the preferred embodiment of the invention, numbers are normally held in a modified dinary representation, the modification consisting merely of the fact that the displacement of the binal point necessitated by the -abovementioned division by two is not followed, so that the effective definition of a number Yr held in a register is:

It is clear that in the preferred embodiment of the invention, eachA register may comprise merely a sequence of storage cells or storage stages, each cell or stage being capable of storing a single bivalued signal representing the corresponding digit of the Y, or R1 number stored in the register. In each operation z', as discussed above, these stored signals are modified in accordance with the inputs to computing circuit 12 to represent the modified numbers Yi+1 of RM1.

As hereinbefore stated, in the preferred embodiment of the invention to be described bereinbel'ow, the operations performed upon. the Y and R numbers are similar in some respects to those utilized in an ordinary digital integrator. They include an integration or summation of applied AY increments in the Y register (so thatv f(Y, AY) simply equals Yi-l-AYi); a multiplication of the function g(Y, AY) of the Y number by the AX increment and an addition of the resultant function to the R number; and the formation of a AZ overow increment which is subtracted from the R register. However, each of these operations has been radically changed to mechanize the acceptancel of input increments which regularly vary in yscale and to mechanize the formation of AZ output increments which similarly vary in scale.

More particularly, in the integration or summation to the Y number of AY increments, which are successively halved in scale, apparatus is provided'for adding each successive AY increment to the Y number at a different position in the Y'register, corresponding to the changing scale of `the AY increments. Thus, in a computational sequence, the first AY increment AY1 is added to the Y register at a position corresponding to a scale of Ve, the second AY increment AY2 is added to the Y register at a position corresponding to a scale of 1A, and so on, until all of the scaled increments have been summed in this manner to the Y number. A brief numerical example will illustrate how this operation is carried out.

Assume that -at the beginning of a computational sequence the number zero (represented in the machine notation as 1.000 is set into the Y register as the initial Y, number Y1. Assume further that during successive operations l, 2, 3, 4 the corrpondingly successive Y, increments applied are AY1=0, Av2: +1, AYP- 1, AYP-1 where the scale of the. successive increments is understood to be 1/2, 1A, Ms, JAG' etc. The following table, Table l, summarizes the formation of successive values of Y1 in response to these increments.

In Table 1, the vertical arrows indicate Ithe varying points at which each successively scaled AY, increment is summed to the corresponding Y1 number. It is seen that, in the dinary notation utilized and for increments successively halved in scale, the point of insertion of the increment is moved or shifted one digit to the right at each timing interval.

Although many methods may be utilized to thus shift the insertion point of successive increments, there is one very simple method, having obvious advantages in ease of the mechanization which is utilized in the preferred embodiment of the invention. According to this method, in order to mark. the successive digit positions at which insertion is to take place, a 1 Value marker signal is initially automatically set in at the 1/2 scaled digit position of the Y number and is moved one digit to the right at each timing interval to thereby indicate the varying points of insertion. Thus, in the actual machine operation the -successive Y, values shown in Table 1 above would actually appear as follows:

where in each case theinsertion point for each increment is indicated by lthe l valued signal which is farthest to the right, and thus serves as the abovedescribed marker signal. The marker signal is, of course, not treated as an ordinary digit of the Y number and is, therefore, not allowed to otherwise aiect arithmetic operations upon the Y number.

It is appropriate at this point to mention that in the specific embodiment of the invention, whose mechanization will be hereinbelow described, the form of summer 18 which is utilized is adapted for summing but two AY input increments, AlYi and A2Y1, and operates to produce a total increment AYi which represents the true algebraic sum of the applied input increments. The following table, Table 2, summarizes the described relation? ship between the values of the input increments and the value of the resultant total increment AY1.

It is seen from Table 2 that in utilizing the described form of summer 18, the total AY increment AY, can assume any of the values +2, +1, V0,k -l, .2, scaled by the appropriate values of 21. It will lbe clear, however, that many other forms of summer 18 may be utilized; as forexample, Vformswhichwtotal agreater numberof AY increments and/ or whichrscale `down the total increment to be in consonance with the inputs.

' "Equations'dening the lat'yovedscribed operations performed inthe preferredembodimentof the invention upon the Y number and upon ythe AY increments are now provided in summarization of the above discussion of these operations. Y

AIYf-il or V(5) AgYir-il OI' 0 Restating Equation 8 in iterative form:

Considering now the manner in which successively applied AX, increments are made effective at their correspondingly scaled values, it will be remembered that, as

stated .hereinbefore, in each operation i, a function g(Y, AY) is multiplied by the-correspondingAX increment and the resultant function is'added to the R number@ In addition, a AZ increment is formed and is subtracted from the R number. This manipulation may be generally summarized by the following equation:

In the preferred embodiment of the invention, whose mechanization is hereindescribed, the function g(Y, AY)

is defined, for reasons which will later appear, as:

However, since AX, and AZ1 are scaled quantities which Y are halved in each timingginterval, a way must be deviscdrto make this scaling effective., This, as will be shown, can be mechanized by halving the Y number at eachV timing interval or by doubling the Ri number at each timing interval. Either process may be largely accomplished by a simple shift of the numbers in the Y and R registers relative to one another, that is by a right shift of the digits of the Y number relative to the R number or by a left shift of the R number digits relative to the Y num-ber digits. In the specific embodiment of the invention hereindescribed, doubling of the R number 12 isvutilized. Thus in this embodiment the equation which is mechanized is:

to the. R number or.V by adding kthe number zero to the R number inraccordance with thevalue AXi. Y That such predetermined scaling is actually made eifective is demonstrated by the following algebraic example in which the operation of a computing block 10, mechanized in accordance with Equation v13 above, is reviewed for three successive operations. Y Y i p At the end of operations 1, 2 and 3, the successive values of R2, R3 and R4 will be:

Now dividing both sidesV by 8 and rearranging terms there is obtained: n f

or writing this in the compressed summation form:

or in the more general case, for any number n of timing intervals in a computation sequence:

Many of the arithmetic operations and other computational activities whichl can be performed with the described embodiment of computing 'block 10 may be deduced from Equation 2O developed above.

In discussing these activities, for reasons which will become clear, it will be assumed that the register number 13 R1 is scaled and maintained so that it is bounded by the numbers +1/2 and -1/2, or in other words, so that:

One set of scaling rules which will accomplish this bounding of the R number is described by the following scaling Equations 22 and 23 which express limitations on the magnitudes of the Y number and upon the summations of the input increments:

and by utilization of the following Rules 24, 25 and 26 which dictate how the overflow increment AZ1 is to be formed, so as to always maintain R1 within its bounded values:

If Ri-l-[Yi-l-l-i Agi equals or exceeds -H then ZF 1 (24) 1 1 If R51-[Ya 2 A 2 r.1st etween a+ and From inspection it will be seen that, in accordance with the foregoing scaling equations, the maximum values of will be bounded by il, and, therefore, that after subtraction of the A21 increment, each new 'value R1+1 of the R number will be bounded, as required, by the values il/z Formation of Y1X+R1.-Referring again to the computational techniques which can be deduced from Equations 8 and 20, there will rst be described an operational sequence involving only a single computing block 10, in which the sequence AZ increments formed Iby the computing block represents the quantity Y1X-l-R1. In performing this computation the number X is represented by the applied sequence of increments AX1, or stated in equation form:

Il Z AX1=X (27) i=1 The increments AX1 may thus be viewed as the successive trinary digits of the number X.

At the beginning of thecomputation'the numbers Y1 and R1 are initially set into the Y and R registers respectively. The increments A1Y1 and A2Y1 are connected as zero inputs so that AY1 is zero, and, therefore (in Equation 8), Y1 is a constant equal to Y1. Thus, in this instance Equation 20 reduces to the form:

However, since the scaling assures that Rn+1 will not exceed il/z, it is clear that the term will not exceed ,and thus is smaller in magnitude than the lowest order la digit of theresult so that it may be ignored. Moreover, since f D E AX 1=X the quantity X may be substituted therefor. In this way Equation 28 reduces to the form:

n E AZiY1X-i-R1 =1 thus demonstrating that in the described operational sequence, the stream of increments AZ1 Will represent the successive digits of the quantity Y1X-|R1.

F ormaton of Y1X.-Note further that if the number R1 set is zero, then Equation 29a further reduces to the form:

n E Z i= Y1X i=1 thus demonstrating that in this case a simple multiplication is performed in which the multiplicand Y1 is held constant in the Y register, the digits of the multiplier X are successively applied (highest order digit rst) as the successive trinary increments AX1, and the corresponding successive trinary digits of the product Y1X are formed as the successive trinary increments AZ1=A(Y1X)1. The number Y1X can 4be obtained in dinary form from the sequence of trinary increments AZ, by summing these increments in accordance with their scale, in the Y register of another computing block. v

The manner in which such a multiplication is accomplished is well illustrated by the simple numerical example provided in Table 3 below:

TABLE 3 Y1=-|%-1.1000 z 2R1= 0 1.0000

Xml-l represented as a stream of applied increments AX; of values In Table 3 above there is provided an example of a multiplication of Y1=+Vz and X :el-V2 (where Y1 is a number initially set into the R register and X `is represented iasa sequence of applied input increments AX1) to form the product Z=Y1X=(|1/z)(+1/z)=l-1A represented by the corresponding sequence of output increments AZ1.

As indicated in Table 3, the numbens initially set into the Y and R registers respectively are 2R1=0 (represented, as indicated by the arrow, in modified dinary as 01.0000) and Y1=+1/2 (represented as 1.1000). The quantity X=+Vz is represented as a sequence of applied increments AX1=+1/2, AX2=0, AX3=0, etc.

During the iirst operation, operation 1, the quantity is added to the quantity 2R1=0 to form the quantity Since Y1AX1 was represented in the form 1+i/z, and 2R1 was in the for-m 1+0, it is clear that represented in the form 2+%.. In accordance with scaling rules (24), (25) and (26), since ziel-Wgr1 is equal to +1/2, the corresponding output increment A21 is +1 (representing AZ1=+1/2) and, therefore, in accordance with Equation 20, the next R number represented in the form 1+(-\V2) as 070.1000). 1n preparation for the next operation R2 is doubled to form 2R2=2(1/2 =1 (represented `as 1+ (-1) or 00.0000).

i During operation 2, the same manipulations are again repeated. Since the quantity and is added (inthe form 1.0000) to 2R2. Since 2R2+Y1AX2= 1 is less than -1/2, the corresponding value ofv AZ2 is -l (representing AZ2=%). subtracting AZZ and doubling, there is obtained 2R3='0.

Therefore, in the continuation of this process it is seen that during succeeding timing intervals onlyvzeroV quan;

' tities are added to the R register, since and also that all succeeding values of AX, are'zero. Thus it is clear that the product Y1X=+1i lis correctly formed Yas the stream of increments AZ1=+1A, AZ2=-%,

Such a summation to establish the number Y1X1 in a register maybe accomplished, as hereinbefore stated, by applying the AZ output increments as AY inputs to an other computing block.

Recognition formulas for formation of AZi and 2R1+1.- Formation of each AZ increment and the corresponding values of 2R1+1, as shown in Table 3 for example, maybe facilitated by operation in accordance with the following simple recognition formulas:

Let the digits which represent the number zliii-l-lvi'l:1 A gi be designated, starting fromthe lowest order digit, as r, 71, r2, 13 rn, r11-E1, rui-2, where rn is the digit to the n'ght of the binal point and rui-1, r11+2 are` the digits to the left of the binalpoint. Thus, for example, referring back to Table 3, in the number representing:

Y' 12R1+Y1A )1=|y- 1" 0 1` 0 0 0 Y Y Y Y y Y n-l- Tn+v1 :n

And for the formation of AZi, the value of each increment may be determined in accordance with the following Boolean equations:

of theA number 2R1+1 is always 0, the digit R1+1n+1 is theV opposite or complement of the digit rn and each of the remaining new digits Ri+11 Rn is found as a result of a left shift of the corresponding digits r r11-1.

It is further seen that if r11+1 and rn have diierent values, AZi will be +1 or =1 in accordance with the l or 0 value respectively of rn+2, While rn+1 and rn have the same values, AZi will be 0. Y

The applicability of these formulas may be readily veried by reference to the example provided in Table 3. It is seen that, during each operation z', the values of AZi and of 2R1+1 may be obtained by applying these formulas to the digits of 2R1+Y1AX1- Computing with assemblages of computing blocks.- Referring now to FIG. 2, there is shown an assemblage of computing blocks 10-1, 10-2, 10-3 1li-j and lil-j+1 interconnected for the performance of a plurality of multiplications and/or additions of the types described hereinabove.

setting desired numbers into the Y and R registers of each of the computing blocks, are supplied to each of the computing blocks by la source of setting signals 31. As indicated in FIG. 2, through cooperative action of sources 30 and 31, at the beginning of a sequence of computational operations, signals representing predetermined numbers A1 A2 A3 Aj are stored -as Y1 numbers of computing blocks 10-1 through lll-j, respectively, and signals representing predetermined numbers B1, B2 B3 Bj are stored as'the R1 numbers of these computing blocks. The number Y1=0 is stored in computing block 10-j+1. Y

A source of stream signals` 32 is operable during a computational sequence for providing signal streams representing predetermined rsequences or streams of increments and, :as shown in FIG. 2, provides a signal stream of increments A(A0)i representing successive digits of a predetermined number A0, and also provides a stream of 0 valued increments, Which are utilized as A1Y and A2Y inputs of various computing blocks. The time at which each increment of signal stream 4is produced by source 32 is As illustrated in FIG. 2, Y' the stream lof increments A(Ao), formed by source 32 is applied to the AX input of computing block 10-1. The stream of 0 valued in- Rules lfor formation of 2R1+1 andY As shown in FIG. 2, timing signals TS for the sequencing of these computations are ksupplied to each lof the computing blocks by .la source of timing signals 30, While setting signals SS for initially 17 crements formed by source 32 is applied to the AlY and A2Y inputs of each of the computing blocks 10-1 through .l-11 As further shown in FIG. 2, the AZ output of computing block -1 is coupled to the AX input 18 10-7 in accordance with the preferred parallel mode of sequencing is illustrated in the following table, Table 4, wherein the increments yformed by source 32 and block 10-1 through NLS are tabulated for eleven successive of block 10-2, and in the same way the AZ output of 5 operation TABLE 4 PARALLEL SEQUENCING Increment Operation times supplied the corresponding bracketed quantities are: [(AeAr-l-BMAg-i-Brl, [[(AoAr-l-BiNAa-l-BdAs-l-Ba,

each block 10-2 through 10j1 is coupled to the AX input of the succeeding block 10-3 through 11i-j, respectively. The AZ `output of block 10-1' is connected to the AlY input of block 10j+1 and the 0 Valued input stream is connected to the AZY input of block lil-j+1.

There are at least two important ways in which the operations of source 32 and of computing blocks l0 may be sequenced under the control of timing signals provided by source 30.

In the rst and preferred mode of sequencing, designated the parallel mode of sequencing, successive increments A(A)i `of the number A', are formed at a rapid rate (at a rate of one increment per operation time) by source 32 and are applied as successive AX inputs to computing block 10-1.

As hereinbefore explained, in response to the rst applied increment A(A)1 and with only one operation time delay, computing block 10-1 forms the corresponding highest order digit A(AA1}B1)1 of the number ADAl-l-Bl, this increment being applied, as soon as it is formed, as the AX input -to block lil-2 which in turn forms the highest `order digit A[(A0A1+B1)A2+B2]1 of the number (AoAl-i-BQAz-i-BZ. In the continuation of this process, each successive computing block forms the highest order digit of the intermediate answer associated therewith and applies this digit to the succeeding computing block, so that after a delay of only y' operation times from the application of the highest order digit of the number A0, the highest order digit of the nal answer is formed by. computing block lll-j and is applied as a AY input to block 10-jll for accumulation therein.

It is clear that in this operation, digits of the final answer are formed by block 10-j at the same rate at which digits of the input number A0 are applied, each computing blockcontributing a delay of only one operation time between the application of an input digit and the formation of ra correspondingly scaled output digit. This feature is common to both modes of sequencing.

In the preferred mode of sequencing, however, because of the rapid rate at which input digits A(A0)i are being r applied, a type of parallel loperation is obtained in which eventually all or nearly all of the computing blocks are sent into simultaneous operation so that earlier computing blocks are operating upon lower `order digits at the same time that later computing blocks are forming higher order digits. This parallel type of` sequencing is best illustrated by considering a speciiic example.

Assume hereafter that in FIG. 2, only -ve computing blocks are cascaded (j=5) and that computation is to be carried out to six significant digits. The way in which digits are formed by source 32 and blocks 10-1 It will be noted, referring to Table 4, that in accordance with the described parallel mode of sequencing, many computing blocks may simultaneously be maintained in operation. For example, during the sixth operation time, all of the computing blocks 16L1 through lib-5 are simultaneously in operation, block 10-5 supplying the rst or highest order digit of the final answer at the same time that blocks 10-4 through 10-1 are supplying the second, third, fourth and ifth order digits respectively of their intermediate answers.

lt is evident that in this parallel mode of operation, extremely high computational speeds are obtained even for great numbers of successive multiplications and additions.

A good understanding of the speed of such operations, relative to that found in the prior art, may be obtained by considering that special case or situation in which each of computing blocks 10 performs only a multiplication (rather than a multiplication and an addition). This situation effectively exists when the R1 numbers are all set in as 0 valuesthat is when B1=B2=B3 In this situation computing block lit-l forms A(A0A1|-O) or A(ADA1) and in similar fashion computing blocks lil-2, lit lil-j form, respectively, A(AA1A2), A(AOA1A2A3) A(AQA1A2A3 Aj). 'Th1-1S, each computing block performs only a multiplication. The

Vfollowing table, Table 5, compares the time required to complete a plurality of multiplications, as performed by either corresponding plurality of cascaded computing blocks as shown in FIG. 2, or by a corresponding plurality of conventional multipliers. It is assumed that the multiplications are carried out to n significant digits.

TABLE 5 Number of operation times Number j o required for completion of multiplcamultiplications tions performed Cascaded Ordinary computing multipliers blocks j=1 n n ]:=2 n+1 2n J=3 n+2 37 j=4 nfl-4 47:

j=n n-l-n n2 The great speed disadvantage of conventional multipliers arises from the fact thatin each such multiplier an entire n digit multiplication must be completed before the result can be utilized in a succeeding multiplier (since eachrdigit is subject to change until the multiplication is completed),

2@ source 30 will be provided at a later point in the specication, computing blocks 10 and sources 30,731 1and 32 will be provided also. l

Qualitative discussion of the described parallel and serial modes of sequencing of computing blocks 10-1 through 10a-j, as `shown in FIG. 2, is now completed. l

Detailed description of the manner in which Vsuch sequencwhile in contrast with the cascaded computing blocks of However, it is useful at this time to generally pointy the present invention, the digits -formed `are not subject out one suitableA form of source 32, which acts as a pri'- tochange and 4are immediately utilizable by succeeding mary source of input increments. Although it will becomputing blocks. Y come clear that source 32 may have many forms well Referringrnow to the second principal mode of seknown to the art, in its preferred form source 32 prin-` quencing, the operations of source 32 and computing 10 cipally `comprises a plurality of computing blocks 10, so blocks -1 through lil-6 (it being assumed as beoperated as to convert numbers periodically stored there-r fore that j=5), in this mode of sequencing input increin into required sequences of increments.

ments A(A0)1 are supplied by source 32 at a slow enough Thus, for example, as shown in FIG. 2, source 32 is rateyso that there is no parallelvoperation of the computseen to include a computing block 10-0 which is operable ing blocks. Y Y under the control of setting signals SS provided by source In this mode of sequencing, which is referred to herein- 31 andV timing signals TS provided by source 32 to pro- Y after as a serial lmode 4o sequencing, after the increment vide the sequence of increments A(A0)1. YAs indicated in A,(A0)1, represen-ting the highest order digit ofthe number FIG. 2, only 0 valued increments kare applied to the AXV A0 is applied, formation and application of a second ininputs of block l0-0. The value initially set into vthe R put digit is delayed until all operations upon the tirst register of the block at the'beginning of each computadigit have been completed and the resultant highest order tional sequence is R1=A0 (set in, in the form 2R1=2A0). digit of the final result is formed by block lil-5. In con- The initial values of Y1 and the values of the AY incretinuing operation, in the same Way, each of the successive ments are not material in this application. However, as input digits is applied ,and each of the corresponding reshown in FIG. 2, AlY and A2Y have 0 values and Y1=0. sultant digits is produced in response thereto. In kthe Since for computing block 10-0, R1==A0 and AX1=0, sequenti-al mode of operation' the computing blocks opby substituting these values in Equation 28 developed erate one after the other, rather than`in any parallel or hereinabove, there is obtained the resultant equation; simultaneous operation. This is illustrated in the followl n ing table, Table 6, which present-s, for the described serial y ZAZigRIAO (38) mode of operation, the increments formed by source 32, z=1 Y and blocks 10-1 through 10-5, during thirteen successive I A operation times, it being assumed las before that 1:5. from which 1t can b inferred that' It is also assumed that B1=B2 =B5=0, so that AZ1=A(A0)I (39) only simple multiplications (rather than combined multi- Y plic'ations and additions) are being performed, and it is as- 35 thus demODSI'fltlllg that block 1.0-0 111 OPel'alOD Wll PIO- lsnmed that input increments A(A0)1 .are applied every duce the requlfed Sequellee 0f mejemells A(Ash, l'ePfe' sevenoperation times during an operational sequence so Senlmg the Dumber Ao mltleuy Set Inte fhe'R register. Y that suiiicient time is allowed for the completion of op- AS further ShOWIl in FIG- 2, IlChe Stream 0f 0 Valued erations upon one input digit before application of the increments supplied by source 32 is provided by a source next input digit. f 40 unit 40. It will be appreciated that unit '40 may comprise TABLE 6 SERIAL SEQUENCING n Operation times supp e y 1 2 s 4 5 6 7 Source 32 MAG);

Block lll-1 AtanAl);

Block 10-2 A(AoA1A.z)1

Block nts--- Antoni/ina Block 10-'4- A(AuA1AzA3A4)i l Operation times Incaregts supp e y s s 1o 11 12 13 Source 32 A(Ao)n Block 10-1 A(A0A1)s B1ok1a2 Ammin),

Block 10-3- Y A(AuA1AzA3)z :Block 10-4- A(AOA1A2A3A4)z Block 10-3 MAoiAzAeAtAs):

a computing block 10 operated in the same manner as block 10-0, but with 1R1=0 set in as an initial value.

However, in the speciiic form of the invention described hereinbelow, constant valued increments are more easily Y ing is obtained under control of timing signals supplied by generated. In the specific form -of the invention to be Detailed description of specific embodiments of Y described, any increment may be represented by two bilevel voltage signals U and V. Signal U at its high and low voltage levels (voltages VH and VL) represents the plus (-1-) and minus values of an increment while signal V at its high and low voltage levels represents the 1 and 0 values of the increment. Thus, as shown in FIG. 2, constant valued increments are represented by signals U0 and V0 at their high and low levels, respectively, signal Uo being formed on a conductor connected yto a source (not shown) of high voltage VH and signal V0 being formed on a conductor connected to a source (not shown) of low voltage VL. Complementary signals U0 and V0 may be similarly formed.

Before beginning detailed description of specic embodiments of block yand sources 30, 31 and 32, one further important example of computation with assemblages of computing -blocks will be described. In this example two streams of increments are electively multiplied by one another to form a stream of increments representing their product. More particularly, a stream of increments, A(A0)i, representing the digits of a number B0, to form -a resultant stream of increments A(AUB0) representing the digits of the product ABO, these increments being accumulated to store the product A0B@ in a register.

Referring now to FIG. 3, there is shown an assemblage of computing blocks 10-1, 10-1', and lil-2. interconnected for performing the abovedescribed multiplication of streams A(AD)1 and MBO), which, as shown in FIG. 3, -are applied thereto by a pair of computing blocks IiP-0 and 1li-0', respectively, contained in source 32. All computing blocks are sequenced under the control of timing signals TS provided by source 30 While appropriate signals SS lfor utilization in the setting of initial conditions into the computing blocks are provided by source 31.

As shown in FIG. 3, blocks 10-0 and 10-0 are operated -in the manner hereinbefore described to act as sources of the sequences of increment A(A0)1 and A(B0), respectively. To this end, initial values of R1=A0 and R1=B0 are set into the R registers of blocks 10-0 and lil-0', respectively, with O valued increments being ap- .plied as the AX inputs to these blocks.

Increments A(A)1 are applied to the AlY input of block 10-1 and to the AX input of block lll-1. Similarly increments A(B)1 are applied to the AIY input of block `10--1 and to the AX input of block 10-1. Zero valued increments lare applied to the AZY inputs of blocks 10-1 and 10-1'. The AZ outputs of computing blocks 10-1 and 10-1' are connected to the A1Y and A2Y inputs, respectively, of computing block 10-2. As shown in FIG. 3, within block v10-2,-the increments AZ, and AZ',` supplied by these outputs of blocks 10-1 and 10-1, respectively, are summed by summer 18 to produce corresponding total AYi increments which as hereinbefore explained, are accumulated in the Y register of block 10-2. As indicated in FIG. 3, the initial value set in of the Y number is Y1=0, so that the value of the Y number after n iterations is 22 Restating this in mathematical terms, it will be demonstrated that for block 10-2 the iinal value Yn+1 of the Y number at the end of a sequence of operations is:

From a consideration of FIG. 3, it is clear that for block 10-2 AY,=AZ,|-Az1 (42) Where `as indicated in FIG. 3, AZ, is the designation of the output increments produced by block 10-1 and AZ1 is the designation of the output increments produced by block E10-1. Combining Equations .40 and 42 there is obtained:

From a consideration of Equation 20 and the substitution of appropriate input quantities, it is seen that for block 10-1:

The summation on the right side of Equation 47 may readily be evaluated. By rearranging terms there is obtained: KHFAYFIMM#Marwua/treuil Aarem 48) which, from a knowledge of nite differences is recognized to be equivalent to the Storm:

Where A(A0B0), is the increment to the product Ao at the ith interation. It is, therefore, clear that n ZA (AoBo) i=AoBo z=1 and, therefore, by substitution in Equation 49 the required result is obtained, namely, that:

and, therefore, the iinal number Yn+1 accumulated in the s Y register of block 10-2 at the end of an operational sequence will be the product ABG.

In connection with Table 7, it is assumed that the numbers A0 and B0, Which are to Ibe utilized, have the values Ao=l3%4 and B0=7A6, .the quantities 2An=2(3%4), therefore, being initially set into the R register of block 10-0, and the quantity 2B0=2(-%6) being initially set into the R register block 10-0. Table 7 shows quantities appearing -in or associated with blocks 10-0, l0-0', 10-1, lil-1', and v10-2 (as shown in FIG. 3) for the first six computational operations of each of the blocks. 

